Electrical Test & ATE Engineer

About the role

Touchdown is engineering the manufacturing behind storage, memory systems, and other chips. This role helps turn a buyer's physical result into a qualified process or a defensible decision to use an existing supplier. Advanced packaging is our intended first fab class; no production fab is operating today.

You will translate product requirements into electrical tests that can reject a bad part and explain why. Define probe or package-test interfaces, fixtures, limits, calibration, binning, data capture, and correlation to system use. Compare existing test capacity before proposing owned equipment. A passing test is meaningful only when coverage, measurement uncertainty, and escape risk are explicit.

Responsibilities

• Define known-good-die evidence, package/interconnect test, fixtures, coverage, and accept/reject decisions.
• Define incoming known-good-die evidence and final package electrical acceptance.
• Design fixtures, test programs, limits, coverage, calibration, and correlation across sites.
• Link failing pins, nets, power, timing, and thermal conditions to physical failure analysis.
• Build tests that distinguish product defects from fixture, contact, instrument, or software failures.
• Review guard bands and sampling with product, quality, and reliability owners before a release limit is changed.

Requirements

Wafer, die, package, and system-level test where relevant; ATE programs, fixtures and load boards, parametric limits, timing and power measurements, test coverage, binning, correlation, calibration, yield, and failure-analysis handoff.

Representative outputs include:

• A test-coverage and correlation plan tied to customer CTQs and downstream failure modes.
• A test specification with vectors, limits, guard bands, coverage, and disposition rules.
• A correlation study between incoming die, post-assembly, and reliability test.
• A test-program revision and correlation packet covering fixtures, calibration, limits, bins, coverage gaps, false rejects, and escape risk.

Qualifications

• Wafer or package test, ATE, signal integrity, test correlation, and product debug.
• Built or qualified wafer, die, board, or package ATE programs.
• Can debug fixtures, signal integrity, contact resistance, and false rejects.
• Can connect test coverage to product use conditions and downstream escape risk.
• Experience developing, validating, or sustaining electrical test programs and hardware interfaces.
• Ability to interpret test distributions, debug test escapes, and communicate limits to product and