Elect Design and Analy Engr

Day to Day Responsibilities

• Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog.
• Develop self-checking and reusable test benches from the ground up, employing Object-Oriented Programming principles such as Inheritance and Polymorphism, while utilizing UVM to build drivers, monitors, predictors, and scoreboards.
• Create Functional Coverage Models and conduct Code Coverage analysis to ensure thorough verification of designs during simulation.
• Set up regression tests and collect coverage metrics to ensure comprehensive verification and track progress over time.
• Assist in FPGA-based prototyping and validation based on program and system requirements and complexity.
• Collaborate with cross-functional teams to ensure that verification strategies align with overall project goals and timelines.

Required Skills & Qualifications

• Proven experience in ASIC/FPGA verification processes.
• Familiarity with defining the architectural framework for ASIC/FPGA verification using SystemVerilog/UVM, including the delivery and release of production designs.
• Proficiency in hardware verification languages, particularly SystemVerilog and SystemVerilog Assertions.
• Demonstrated experience in implementing test plans effectively.
• Solid understanding of Object-Oriented Programming principles, such as Inheritance and Polymorphism.
• Capability to design self-checking and reusable testbenches from the ground up.
• Experience in developing Functional Coverage Models and achieving Code Coverage closure.
• Capable of collaborating with design and system engineering to establish accurate and verifiable ASIC/FPGA level specifications.
• Familiarity with waveform debug tools.
• A Bachelor of Science degree in Engineering (specializing in Electrical, Mechanical, or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry, or equivalent non-US qualifications relevant to the job description.

Preferred Skills & Qualifications

• Experience with hardware-based integration and test of ASIC/FPGA designs.
• Experience with hardware emulators, especially Palladium.
• Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet).

Pay & Benefits

Pay range: Between $75 per hour–$80 per hour.

Benefits (based on eligibility) include: Medical & pharmacy coverage, Dental/vision insurance, 401(k), Health saving account (HSA) and Flexible spending account (FSA), Life Insurance, Pet Insurance, Short term and Long term Disability, Accident & Critical illness coverage, Pre-paid legal & ID theft protection, Sick time, and other types of paid leaves (as required by law), Employee Assistance Program (EAP).

This response is AI-generated, for reference only.