Director, Design Verification

About the role

The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash. DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions such as Custom HBM base die, AI accelerators. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

Responsibilities

• End-to-end verification of SoCs
• Manage a highly capable team of engineers driving the first-pass silicon success
• Define and implement SoC verification strategy and methodology
• Lead the team to successful verification signoffs
• Plan and manage resource over multiple concurrent projects
• Participate in defining & enhancing development milestones and flows for SoC projects
• Work closely with Architecture, Design, FW, Validation counterparts to align on verification requirements and targets
• Provide support in post silicon bring up and debug

Requirements

• Bachelor’s (MS preferred) in Computer/Electrical Engineering or Computer Science with 15+ years working experience in ASIC verification preferred
• Several years of proven leadership in verification team management
• Experience in multiple successful tape-outs
• Demonstrated ability to manage complex project schedules, resource allocations and risk mitigations
• Expert level knowledge and experience in UVM, c++, and SystemVerilog
• Expert level knowledge in verification flows and tools
• Excellent verbal and written communication skill
• Self-motivated problem-solver with an ability to work well in a team

Qualifications

• Inclusive, adapting your style to the situation and diverse global norms of our people
• Avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding
• Collaborative, building relationships, humbly offering support and openly welcoming approaches
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

Skills

• UVM
• c++
• SystemVerilog

Benefits

We offer a comprehensive benefits package including:

• Medical/Dental/Vision coverage
• 401(k) retirement plan
• Charitable giving match
• Flexible vacation policy
• Support for family and pet wellness
• On-site amenities and wellness programs

Pay

$219,000—$351,000 USD

Schedule

Daily onsite presence in San Jose HQ location 5 days a week