Digital Verification Manager

Responsibilities

• Lead end-to-end verification of digital subsystems (testbench architecture, UVM development, functional and code coverage closure, formal verification, CDC/RDC sign-off, low-power verification, gate-level simulation, and emulation/FPGA prototyping), ensuring aggressive schedule targets are met without compromising quality.
• Define and enforce verification plans, sign-off criteria, and silicon-correlation strategies that catch bugs pre-silicon and drive first-silicon success.
• Manage, mentor, and grow a high-performing, multi-site team of 6–12 verification engineers. Own goal-setting, performance reviews, career development, and hiring across sites, while fostering a culture of accountability, collaboration, and continuous improvement that holds up across time zones.
• Drive seamless collaboration with design, architecture, analog, DFT, firmware, post-silicon validation, and test teams to keep programs moving fast and aligned from spec → vplan → implementation → sign-off → bring-up.
• Define and track aggressive verification schedules, compute and license resource plans, and risk-mitigation strategies. Communicate progress, coverage status, trade-offs, and escalation paths clearly to executives and customers.
• Provide architectural guidance for verification environments targeting high-speed digital subsystems, including multi-lane data paths, clocking and reset schemes, and mixed-signal control loops (real-number modeling and AMS co-simulation).

Requirements

• 10+ years of digital ASIC verification, with at least 3 full product cycles successfully executed from specification to high-volume production.
• Proven track record of driving on-time, first-silicon success on complex, high-performance ASICs with mixed-signal interfaces (e.g., SerDes, DACs/ADCs, RF SoCs, display/camera pipelines).
• Strong expertise in SystemVerilog/UVM, constrained-random verification, functional coverage, SVA assertions, formal property verification, CDC/RDC sign-off, low-power verification (UPF/CPF), gate-level simulation, and emulation/FPGA prototyping.
• Understanding of mixed-signal verification and ability to partner effectively with analog and design teams on specification splits and verification ownership.
• Demonstrated success in line management and performance management, including hiring, mentoring, and building high-performing verification teams.
• Skilled in fast-paced, cross-functional program leadership with a proven ability to manage schedules, risks, and EDA vendor/tool relationships.
• Outstanding written and verbal communication; confident presenting clear, concise verification status, coverage data, and risk assessments to executives, customers, and cross-site teams.

Qualifications

• Proven track record of driving on-time, first-silicon success on complex, high-performance ASICs with mixed-signal interfaces (e.g., SerDes, DACs/ADCs, RF SoCs, display/camera pipelines).
• Strong expertise in SystemVerilog/UVM, constrained-random verification, functional coverage, SVA assertions, formal property verification, CDC/RDC sign-off, low-power verification (UPF/CPF), gate-level simulation, and emulation/FPGA prototyping.
• Understanding of mixed-signal verification and ability to partner effectively with analog and design teams on specification splits and verification ownership.
• Demonstrated success in line management and performance management, including hiring, mentoring, and building high-performing verification teams.
• Skilled in fast-paced, cross-functional program leadership with a proven ability to manage schedules, risks, and EDA vendor/tool relationships.
• Outstanding written and verbal communication; confident presenting clear, concise verification status, coverage data, and risk assessments to executives, customers, and cross-site teams.

Skills

• SystemVerilog/UVM
• Constrained-random verification
• Functional coverage
• SVA assertions
• Formal property verification
• CDC/RDC sign-off
• Low-power verification (UPF/CPF)
• Gate-level simulation
• Emulation/FPGA prototyping
• Mixed-signal verification
• Real-number modeling
• AMS co-simulation

Benefits

• Competitive Salary: Commensurate with your experience, skills, and location
• Equity & Ownership: Meaningful stock options
• Proximity Bonus: Annual Living-Local Bonus if your residence is within 20 minutes of the office
• Retirement Benefits: Employer-contributed retirement plans to help you build long-term financial security

Pay

Competitive Salary: Commensurate with your experience, skills, and location

Schedule

N/A