Digital Verification Engineer 2 - 23340 (FS Poly Required)

Job Description

Candidates will develop models, transactors, stimuli, monitors, and test benches for simulating and uncovering hidden behaviors in gate-level digital netlists. Candidates will be expected to produce clear documentation and test cases demonstrating identified bugs or deviations from the specification. Effective collaboration with teammates to produce cohesive results and create improved processes is required.

Essential Job Responsibilities

• Develop models, transactors, stimuli, monitors, and test benches for simulating and uncovering hidden behaviors in gate-level digital netlists.
• Produce clear documentation and test cases demonstrating identified bugs or deviations from the specification.
• Collaborate effectively with teammates to produce cohesive results and create improved processes.

Minimum Qualifications

• 2 years relevant experience with Bachelors in related field; 0 years experience with Masters in related field; or High School Diploma or equivalent and 6 years relevant experience.
• US Citizenship
• Active DoD Top Secret/SCI with Full Scope Poly at the time of consideration
• Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• Experience with modern digital verification and modeling languages: SystemVerilog, SystemC, C/C++, Matlab, etc.
• Directed, constrained-random, and assertion-based verification techniques at the gate, interface, and transaction levels
• Experience with modern, commercial-grade, functional simulators (e.g., Xcelium, Incisive, Questa, VCS, Riviera-Pro, etc)
• Writing scripts for batched verification tasks: Python, Bash, Tcl, make files.
• Revision control systems for maintaining, sharing, and deploying code: Perforce, git, SVN, etc.
• Familiarity with debugging and isolating issues with gate-level netlists

Preferred Requirements

• Familiarity with object-oriented, embedded, assembly, or machine code programming
• Software or hardware reverse-engineering (e.g., IDA Pro, Ghidra)
• FPGA design or verification
• Familiarity with testing and verification techniques for IC trust, assurance, or security
• Experience with logical equivalence checkers (e.g., OneSpin 360-EC, ESP, Conformal EC)
• Experience with formal ABV

Physical Requirements

May require working in an office, industrial, shipboard, or laboratory environment. Capable of climbing ladders and tolerating confined spaces and extreme temperature variances.