Design Verification Engineer (Silicon Engineering)

Responsibilities

• Write and review test plans, develop test harnesses and test sequences
• Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks
• Execute test plan, run regressions, and achieve code and functional coverage closure
• Automate test case generation using Python and MATLAB programs
• Contribute to pre-silicon verification, chip bring-up, and post-silicon validation

Qualifications

• Bachelor’s degree in electrical engineering, computer science or computer engineering
• 1+ years of experience with design verification and test bench development

Preferred Skills and Experience

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience