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Design Verification Engineer - Interface IP

Etched · San Jose, CA · Yesterday
On-siteEngineering$150k–$275k/yrFull-time

About the role

We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.

Key Responsibilities

  • End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
  • Understand vendor IP configurations and handle handshake with internal IP team
  • Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications
  • Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture
  • Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios

Requirements

  • 5+ years of design verification experience
  • Enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs
  • Have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches
  • Are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs
  • Thrive in a fast-paced startup environment and can take ownership of projects with minimal direction
  • Collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights

Qualifications

  • Strong Candidates May Also Have Experience With
  • Experience handling vendors and integration of IP/VIP’s
  • UVM/System Verilog

Benefits

  • Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
  • Housing subsidy of $2k per month for those living within walking distance of the office
  • Relocation support for those moving to San Jose (Santana Row)
  • Variety of wellness benefits covering fitness, mental health, and more
  • Daily lunch + dinner in our office
  • Unlimited compute budget subject to ROI justification

How We’re Different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

Pay

Compensation Range: $150K - $275K

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