Design Verification Engineer

About The Role

Intel is seeking a New College Graduate Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to the verification of next-generation interconnect and chassis IPs that underpin Intel's most ambitious SoC and platform products. You will work alongside senior engineers to build testbenches, write constrained-random tests, close functional coverage, and root-cause simulation failures — developing end-to-end verification skills from day one. We look for engineers who think algorithmically, write clean code, and are excited to apply the latest AI-assisted development tools as a core part of how they work.

Key Responsibilities

• Develop testbench components, constrained-random stimulus, and functional checkers for interconnect and chassis IP under guidance of senior engineers
• Write, run, and debug simulation tests; analyze failures and root-cause issues to closure with clear technical write-ups
• Contribute to functional coverage plans, coverage closure analysis, and regression triage
• Participate in spec reviews, design discussions, and bug triage; learn to contribute across architecture, design, and software boundaries
• Use AI-assisted coding and debugging tools as an everyday part of development workflow; actively contribute to the team's productivity through automation and scripting
• Continuously build depth in hardware design, verification methodology, and the chip development flow

Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, or Computer Science
• Strong foundation in logic design and digital circuits; ability to read and reason about RTL is essential
• Strong algorithmic thinking and software fundamentals; demonstrated proficiency in at least one of C/C++, Python, or SystemVerilog through coursework, projects, or internships
• Coursework or project exposure to two or more of the following: computer architecture, parallel and distributed computing, operating systems, hardware/software interfaces, or VLSI design
• Demonstrated use of AI coding assistants as a regular part of coursework or project work — not occasional use, but as a genuine productivity tool
• Internship or research experience in a hardware design or verification environment

Preferred Qualifications

• Coursework or project work in hardware verification, FPGA design, or RTL simulation (ModelSim, VCS, Questa, or similar)
• Exposure to SystemVerilog, UVM concepts, or assertion-based verification through coursework, self-study, or internship
• Familiarity with standard bus protocols (AXI, AHB, PCIe) or cache/memory hierarchy concepts
• Comfort working in Linux environments, using version control (git), and writing build/test automation scripts
• Demonstrated project work (senior design, research, hackathon, or personal) involving hardware modeling, algorithm implementation in HDL, or hardware-software co-design