Design Verification Engineer - AI Accelerators

About the role

Reality Labs focuses on delivering Meta's vision through Augmented Reality (AR) and Smart Devices. Compute power requirements of these devices require custom silicon. Meta’s Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body.

As a Design Verification Engineer at Meta’s Reality Labs, you will work with a multidisciplinary group of researchers and engineers, and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP implementations and contribute to development and optimization of state of the art machine learning algorithms.

Responsibilities

• Work with cross-functional leads, including product managers, systems architects, researchers, and software architects, to develop industry leading Machine Learning IP’s optimized for Mixed Reality and Smart Devices and use-cases, defining verification methodologies for each of the different core IPs
• Define, track, and lead the execution of detailed test plans for the different modules and top levels
• Implement scalable test benches including checkers, reference models, assertions in System Verilog
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
• Collaborate with cross-functional teams such as Design, Model, Emulation and Silicon validation teams towards ensuring design quality targets are met across pre- and post-Silicon product lifecycle
• Support hand-off and integration of developed subsystems/IP blocks into larger SOC environments
• Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Qualifications

The minimum qualifications for this role include:

• 10+ years of hands-on experience in SystemVerilog/UVM methodology and C/C++ based verification
• 10+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
• Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
• Track record of 'first-pass success' in ASIC development cycles
• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

The preferred qualifications for this role include:

• 5+ years of experience with Design verification/validation of machine learning applications and accelerators
• 5+ years of experience with Software/Hardware Co-design at firmware, ISA, and application level
• 5+ years of experience with low power design
• 5+ years of experience in verification of numerical compute based designs
• Experience with revision control systems like Mercurial(Hg), Git
• FPGA/emulation debug experience

Pay

Individual compensation is determined by skills, qualifications, experience, and location, with a salary range of $178,000/year to $250,000/year, plus bonus, equity, and benefits.