Design Validation Test - Lead/Principal Engineer

About the role

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.

Key Responsibilities

• Define a risk-based DVT strategy spanning board/subassembly engineering validation through system integration validation.
• Author and maintain DVT plans, procedures, and reports with crisp pass/fail criteria and coverage rationale.
• Establish stage gates and readiness reviews for execution quality (fixtures, instrumentation, scripts, SW readiness).
• Build and own benchtop and rack-level validation setups that are repeatable and automation-friendly.
• Lead RCA for validation failures; drive corrective actions with design teams; verify fixes through re-test and data review.
• Execute and interpret power integrity/stability measurements (voltage/current stability, droop, ripple/noise, IR drop) and close gaps to requirements.
• Validate high-speed interconnect performance and margin; isolate failures across channel, connector/cable, PHY, and firmware/diagnostics layers.
• Partner with reliability and manufacturing teams to ensure DVT coverage supports ramp readiness and reduces escapes.

Minimum Qualifications

• BS/MS in Electrical or Computer Engineering (or equivalent experience).
• 8–15+ years of hardware validation/DVT experience on complex board and system-level products.
• Demonstrated ownership of board bring-up and DVT execution: test plan creation, instrumentation, debug, and closure.
• Strong background in power delivery validation and measurement (sequencing, margining, droop, ripple/noise, IR drop).
• Strong background in high-speed I/O validation and debug (PCIe/Ethernet-class links; channel and system-level troubleshooting).
• Proficiency with lab equipment: oscilloscopes, logic analyzers, power supplies/analyzers, DC electronic loads; VNAs/BERTs as applicable.
• Strong written and verbal communication; ability to present results and drive decisions with data.

Preferred / Nice-to-Have Experience

• With rack-scale and/or liquid-cooled systems; validation in environmental chambers.
• Experience supporting compliance/safety/EMC efforts as part of DVT readiness.
• Python (or similar) for test automation and data analysis; experience integrating results into dashboards/CI workflows.
• Experience mentoring engineers/technicians as an informal technical leader.