Debug/Trace/Profiling Design Engineer

The Role

SiFive is seeking a hardware design engineer to design industry-leading debug, trace and profiling IP. This role will be crucial to SiFive’s effort to create silicon at the speed of software across our entire IP portfolio.

Responsibilities

• Arcitect, design and implement debug, trace and profiling hardware.
• Work with architecture, performance, software and hardware teams in architecture/microarchitecture exploration and specification.
• Implement RTL generators such that elements self-configure to optimally design-in extensive configurability as a first-class consideration.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
• Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans.
• Ensure that knowledge is shared via creation and maintenance of great documentation and participation in a culture of collaborative design.

Requirements

• Knowledgeable in debug, trace and profiling architecture and concepts.
• Knowledgeable in debug interfaces, JTAG, cJTAG.
• Knowledgeable in CPU architectures, power management and SoC design.
• Experience in debugging tools, profiling methods.
• Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.
• Attention to detail and a focus on high-quality design.
• Ability to work well with others and a belief that engineering is a team sport.
• Knowledge of at least one object-oriented and/or functional programming language.
• Knowledge of one or more of: Chisel/Scala, RISC-V architecture, Git/Jira/Confluence (a plus).
• 7+ years of industry experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high-performance processors.
• MS/PhD in EE, CE, CS or a related technical discipline.