CPU Physical Design Integration

About the role

Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a member of our CPU physical design integration team, you'll drive end-to-end integration, physical verification and final tape-out signoff checks.

Responsibilities

• Lead and/or participate in overall floorplan development and drive area optimization
• Own and develop the end-to-end Physical Design Integration methodology and execution
• Drive and participate in efforts for Physical Verification (PV), PERC, and ESD signoff
• Own bump and RDL design in close collaboration with the internal packaging team
• Own the complete analog interfaces, and custom signal construction and implementation
• Interface directly with foundry and technology teams as required
• Partner with the internal CAD team to develop and maintain the Tools, Flow and Methodology (TFM) across all relevant design domains
• Collaborate with CPU and subsystem unit owners, custom circuit designers, CAD engineers, and RTL teams as needed

Qualifications

• Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in CPU physical design integration
• Experience in multiple tape-outs of SoCs in the latest technology nodes relevant for CPUs
• Deep expertise in Physical Verification, PERC, ESD, Bump & RDL
• Expertise in CPU blocks lego planning based on technology rules
• Experience in Physical design integration methodologies and Signoff process
• Proficiency with Siemens, Synopsys or Cadence EDA tools for Physical Design
• Comprehensive understanding of end-to-end physical design implementation and design closure across all signoff domains
• Strong communication skills with the ability to build processes and infrastructure from the ground up

Skills

• Preferred Experience with PNR (Place and Route) & owning blocks
• Proficiency in scripting languages including Python, Perl, and/or TCL for design automation and flow development