Jobs · Engineering · Texas

ASIC Physical Design Engineer, Netlisting - New College Grad 2026

NVIDIA AI · Santa Clara, TX · 2 mo ago
EngineeringFull-time

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work.

About the role

We are now looking for a motivated ASIC Physical Design Engineer, Netlisting to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, this role involves driving the physical design of high-frequency and low-power CPUs, GPUs, and SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects.

Responsibilities

  • Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, focusing on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, and netlist quality checks.
  • Help in ECO generation and implementation.

Requirements

  • Master's or PhD degree in Electrical or Computer Engineering (or equivalent experience).
  • Proven knowledge in logic equivalence checking/Formal Verification from RTL to tapeout using industry-standard tools.
  • Understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
  • Experience in clock-domain-crossing checking, MTBF analysis, using EDA tools (e.g., Synopsys or Cadence) or in-house tools.
  • Background in logic synthesis at either block or full-chip level, including project execution and/or flow development.
  • In-depth knowledge of industry-standard EDA tools in related fields.
  • Experience with programming and scripting languages such as Perl, TCL, Make, Python, etc.

Skills

  • Experience in logic synthesis and equivalence checking/FV.
  • Familiarity with industry tools and flow.
  • Strong hands-on debugging capability and problem-solving skills.
  • Experience improving workflows and productivity through effective AI utilization is a plus.

Pay

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $116,000 USD - $189,750 USD for Level 2, and $136,000 USD - $218,500 USD for Level 3. You will also be eligible for equity and benefits.

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