ASIC Engineer - Early Career

Multiple positions available across our Business Units. You will be matched with an appropriate engineering team based on your skillset and experience and our current business needs. Applications will be reviewed on a rolling basis.

We prioritize placing early career engineers in locations where they can be co-located with their team and the relevant hardware they support. Please indicate in your application where you would be willing to be located.

Responsibilities

• Contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs
• Support module-level and subsystem-level verification using SystemVerilog/UVM
• Write test plans and functional coverage definitions under guidance from senior team members
• Assist with CDC/RDC/LINT checks and clean-up
• Participate in code coverage and functional coverage closure activities
• Help develop assertions, protocol monitors, and scoreboards for testbenches
• Support integration and verification of external IP (e.g., bus fabrics, standard interfaces)
• Learn and apply industry-standard verification methodologies (UVM, formal verification basics)
• Debug RTL and testbench issues with guidance from senior engineers
• Document design intent, verification results, and test coverage

Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, or related technical field (completed or in final year)
• Coursework or project experience with Verilog/SystemVerilog RTL design or verification
• Understanding of digital logic design fundamentals (combinational/sequential logic, FSMs, timing)
• Familiarity with basic verification concepts (testbenches, simulation, coverage)
• Strong problem-solving skills and attention to detail
• Effective communication and ability to work in a collaborative team environment

Skills

• Academic or internship experience with SystemVerilog/UVM
• Exposure to scripting languages (Python, Perl, Tcl) for automation/tooling
• Coursework or projects involving communications systems, DSP, or FPGA design
• Familiarity with common EDA tools (e.g., VCS, Xcelium, Questa, formal tools)
• Understanding of computer architecture fundamentals (CPUs, bus protocols like AXI)
• Personal projects, capstone work, or research involving digital design/verification (e.g., GitHub repos, senior design projects)

Pay

Base Pay Range:

• For CA applicants: $129,032.00 - $180,644.10
• For WA applicants: $129,032.00 - $180,644.10
• Other site ranges may differ

Benefits

• Medical, dental, vision, basic and supplemental life insurance
• Paid parental leave
• Short and long-term disability
• 401(k) with a company match of up to 5%
• Education Support Program
• Stock Options for all regular employees (working at least 20 hours/week)
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays
• Dependent on role type and job level, employees may be eligible for additional benefits and bonuses

Applicants for employment at Blue Origin must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Background checks are required for all positions. Additional checks may include Defense Biometric Identification System (DBIDS), driver qualification files, medical certification, road tests, drug and alcohol testing, vehicle inspection requirements, CDL requirements, and hazardous materials transportation/shipping training, depending on the role.