ASIC Engineer, Architecture

Location: Austin, TX | Type: Full-time

About the role

As an ASIC Engineer specializing in architecture, performance, and modeling at Meta, you will focus on defining and driving architectural performance analysis and pre-silicon modeling for custom ASICs. Your role will involve collaborating with architecture, design, and software teams to ensure that silicon meets performance targets for Meta's infrastructure. You will also establish methodologies for performance analysis and develop workloads for machine learning applications. This position is critical in shaping the long-term silicon roadmap strategy for Meta's AI and data center workloads.

Requirements

• 6+ years of experience in ASIC design, silicon engineering, or a related technical field.
• Proficiency in C++ and Python for developing simulation models, automation frameworks, and performance analysis tools.
• 5+ years of experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs.
• Experience with performance analysis of data center, AI accelerator, or high-performance computing workloads on custom silicon.
• Experience developing cycle-accurate or transaction-level performance models using C++ and SystemC for complex digital systems.

Responsibilities

• Drive microarchitectural exploration and trade-off analysis across compute, memory subsystem, interconnect, and I/O domains.
• Define and own the performance modeling strategy for custom infrastructure ASICs.
• Develop and maintain C++ models of AI chip IPs and subsystems for architecture exploration and performance analysis.
• Develop low-level workloads and kernels for machine learning training and inference applications.
• Establish performance analysis methodologies, benchmarking frameworks, and bottleneck identification techniques across the full ASIC pipeline.
• Collaborate with architecture, RTL design, and physical design teams to translate performance requirements into implementable microarchitectural specifications.
• Partner with software and systems teams to co-optimize workload scheduling, firmware, and driver behavior against silicon performance characteristics.
• Lead cross-functional technical reviews and communicate performance modeling results and architectural recommendations to engineering leadership.
• Define long-term performance modeling infrastructure roadmaps, including tooling, automation, and simulation platform investments.
• Mentor other engineers on performance modeling techniques, simulation methodology, and microarchitectural analysis best practices.

Benefits

• Comprehensive medical, dental, and vision coverage.
• Mental-health resources, family planning support (fertility, adoption, surrogacy), and caregiving programs.
• Financial benefits including a competitive retirement plan, equity awards, life insurance, and access to financial coaching and legal support.
• Generous PTO and holidays, unlimited sick time, various paid leaves, flexible “Global Travel Days,” and a 30-day paid break every five years.

Pay

$146,000 - $209,000 per year