ASIC Design Verification Technical Leader

About the role

The Design Verification Lead will play a crucial role in defining and leading the verification methodology and standards for multiple projects. This individual will coordinate activities across multiple sites, leading verification at both the block and chip levels, and will review specifications, participate in design reviews, and influence architecture for testability and verification efficiency.

Responsibilities

• Define and lead verification methodology and standards across multiple projects, coordinating activities across multiple sites.
• Lead verification at block & chip level with various high-speed IPs integrated like ODSP, D2D IP, SerDes XSR/PAM4, Integrated drivers/TIA, and control functions.
• Review specifications, participate in design reviews, and influence architecture for testability and verification efficiency.
• Mentor and coach verification engineers, driving continuous improvement in technical skills and execution.
• Debug complex silicon and system-level issues during bring-up phases.
• Support post-silicon bring-up and optimize integration and performance.

Requirements

• Bachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC Design Verification experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience, or PhD in Electrical Engineering or Computer Engineering + 3 years in ASIC Design Verification experience.
• Experience in System Verilog, UVM, and verification methodologies.
• Experience owning and delivering verification for large-scale SoCs or subsystems.
• Experience leading verification teams or projects.
• Experience in scripting and automation such as Python, Perl, TCL, or Shell Scripts.

Preferred Qualifications

• Strong experience with UVM (Universal Verification Methodology) for developing scalable, reusable, and coverage-driven verification environments.
• Expertise in verification of SerDes IP, D2D PHY IP, ODSP & integrated transceiver features, CPU sub-system & Protocols (Ethernet, UCIE, UAL, SPI/I2C, etc.).
• Experience influencing design for testability and verification.
• Proven experience in troubleshooting and debugging.
• Experience with Formal Verification, hardware description languages (HDLs) such as Verilog/System Verilog).
• Experience with emulation and prototyping platforms (Veloce, HAPS).
• Experience collaborating with architecture and design teams on verification strategy.

Benefits

Cisco offers competitive compensation, comprehensive benefits, and a supportive work environment. Starting salary range for this position is $163,600.00 to $234,600.00, subject to location and performance. Additional benefits include medical, dental, and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Employees may also be eligible for additional paid time off, grants of Cisco restricted stock units, and performance-based incentive pay.