ASIC Design Verification Engineer (Santa Clara, CA)

Santa Clara, CA • Full-time

About the role

As an ASIC Design Verification Engineer at Qualcomm, you will be part of a team responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support. Your role will focus on comprehensive pre-silicon test planning for digital power IPs, utilizing advanced verification methodologies such as SystemVerilog-UVM. You will also be involved in developing automation to enhance verification efficiency and deploying power-aware UPF verification flows. This position requires inventive minds to transform 5G's potential into world-changing technologies and products.

Responsibilities

• Plan and execute comprehensive pre-silicon tests for digital power IPs
• Develop testbenches using advanced verification methodologies such as SystemVerilog-UVM
• Create coverage and assertion models for verification purposes
• Involve in formal verification and property checking
• Develop automation tools to improve verification efficiency

Requirements

• Minimum 3 years of DV experience using UVM/assertion based verification technologies
• Experience in verifying complex SOC or SOC subsystems
• Experience with caches and DDR memory protocol verification
• Exposure to firmware/driver development using C++
• Bachelor's degree in Science, Engineering, or related field

Benefits

• Competitive compensation and annual bonuses
• Stock programs
• Comprehensive healthcare coverage
• Retirement plans
• Wellness programs
• Parental leave
• Flexible work options
• Professional development opportunities

Pay

$107,400 - $161,200 per year