ASIC Design-for-Test (DFT) Engineer Intern

About the role

Keysight Technologies is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~16,800 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.

Keysight Technologies has an exciting opportunity for an ASIC Design-for-Test (DFT) Engineer Intern within our ASIC R&D organization. This role provides hands-on experience across the semiconductor product development lifecycle, with a focus on Design-for-Test (DFT) methodologies used to ensure the manufacturability, quality, and reliability of advanced integrated circuits. Working alongside experienced ASIC Test Engineers, you will gain exposure to industry-standard EDA tools and flows used for scan insertion, ATPG pattern generation, memory test, silicon validation, and production test development. This internship is an excellent opportunity for students interested in digital design, VLSI, semiconductor development, and hardware engineering to gain practical experience on real ASIC programs. As an intern, you will collaborate with ASIC design, verification, physical design, and test engineers while contributing to projects that directly impact the successful development and release of next-generation semiconductor products. This position is based in Colorado Springs, Colorado, consistently recognized as one of the nation's most desirable places to live.

Responsibilities

• Support the development and verification of DFT architectures for complex digital and mixed-signal ASICs
• Learn and apply industry-standard DFT methodologies, including scan insertion, scan compression, ATPG, Streaming Scan Networks, and memory BIST (MBIST)
• Assist with ATPG pattern generation, coverage analysis, and debug using Siemens Tessent and other industry-standard EDA tools
• Develop scripts and automation solutions using Python, Ruby, Tcl, or similar languages to improve engineering workflows and data analysis
• Collaborate with AS