Architecture - I/O Architect

Key Responsibilities

• Define NuLink PHY subsystems (physical and logical/link layers) and hierarchical modular protocol bridges between PCIe, AXI4, APB, CHI, CXL (.io/.cache/.mem), DDR to name a few.
• Design protocol conversion layers with transaction ordering, credit-based flow control, QoS, address translation, coherency management, and memory semantics across protocol domains.
• Model and tune PHY data path, link protocols, and CDC architectures for protocol efficiency, bandwidth, latency, power, and signal integrity.
• Conduct technical evaluation and benchmark analysis against internal and external IPs.
• Partner with ASIC, firmware, and post-silicon teams. Support customer integration for compute-to-memory (CXL/DDR), processor interconnect (AXI/PCIe), and control plane (APB).
• Create clear and comprehensive architecture specifications with foolproof integration guidelines.
• Review characterization plans for PLL, VCO, ATB, and link training. Create protocol testbenches validating transaction handling, latency, throughput, and compliance.

Qualifications

• Expertise in multiple areas of architecture definition, chip micro-architecture, protocol definition and implementation.
• Strong knowledge of two or more of the following connectivity protocols - PCIe, UCIe, UALink, Ethernet, DDR, AMBA.
• Strong scripting and automation skills.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years' of experience.
• 15+ years of experience in ASIC architecture with strong bias for practical logic design and influence of physical implementation, with a proven track record of leading teams through successful tapeouts.
• Performance modeling of hardware implementations with high level languages like C, C++, or SystemC.
• Adept at clocking and floorplan guidelines for PHY implementation.
• Exceptional problem-solving skills.