Architect - FPGA Design, AXI/ UCIe Protocol

About the role

Enable top semiconductor and hyperscale customers to validate their next-generation SoCs against real-world devices months before silicon, reducing time-to-market and catching integration issues that simulation cannot find.

Responsibilities

• Design and develop Speed Adapter solutions for PCIe Gen5/Gen6, CXL 2.0/3.x, UCIe, and AXI protocols that bridge real-world high-speed I/O with designs running on ZeBu emulation and HAPS prototyping platforms
• Implement protocol logic and speed adaptation functionality on FPGA-based platforms, managing the translation layer between multi-gigabit real-world interfaces and reduced-speed DUTs
• Develop and debug RTL, firmware, and system-level components across the full Speed Adapter stack, from transceiver configuration to protocol state machines to host integration
• Collaborate with IP teams, emulation platform engineers, and prototyping teams to deliver integrated system-level validation solutions that customers can deploy in their labs
• Build reference designs, example flows, and integration documentation that enable customers to connect their DUTs to real devices, testers, and hosts with minimal friction
• Support customer escalations involving complex system-level issues, performing root-cause analysis across hardware, firmware, and protocol layers to deliver solutions that actually resolve the problem
• Contribute to roadmap planning and feature definition for next-generation Speed Adapter products, including emerging protocols and differentiated capabilities not available from competitors

Requirements

• 12 years+ relevant experience
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent hands-on experience in digital design and FPGA-based systems
• Deep hands-on experience with at least two of the following protocols: UCIe, PCIe (Gen4 or later), CXL (2.0 or later), or AXI, including implementation or validation work, not just integration
• Strong RTL development skills and proven experience designing, debugging, and deploying logic on FPGA platforms in production or customer-facing environments
• Experience with system-level validation, emulation, or prototyping environments where you have worked across the hardware/software boundary to bring up and debug complex systems
• Solid understanding of high-speed serial interfaces, including transceiver configuration, link training, and physical layer bring-up
• Demonstrated ability to debug across RTL, firmware, and board-level hardware, using tools like waveform viewers, logic analyzers, protocol analyzers, and embedded debuggers
• Experience with ZeBu, HAPS, Veloce, Palladium, or similar emulation/prototyping platforms is a strong plus, as is familiarity with In-Circuit Emulation or Direct-ICE workflows

Qualifications

• You can walk into a customer lab where nothing is working, pull waveforms, check register states, and narrow a system-level failure down to a specific protocol violation or timing issue within a few hours
• You write RTL that other engineers can read and maintain, and you care about resource utilization, timing closure, and what happens when the design has to run on a different FPGA family next year
• You are comfortable presenting a technical tradeoff to a senior architect or customer engineering team, explaining why approach A costs more FPGA resources but solves the real-world interoperability problem that approach B does not
• You do not wait for someone else to define the integration plan. You talk to the IP team, the platform team, and the customer, then you write the plan and start building
• You have worked on at least one project where the protocol spec was still evolving, the hardware was not quite ready, and you had to build something that worked anyway
• You treat customer escalations as opportunities to understand the real problem, not just close the ticket, and you follow through until the solution is validated in the customer's environment

Skills

• Protocol specification knowledge
• FPGA design and development
• RTL design and debugging
• System-level validation
• High-speed serial interface expertise
• Emulation and prototyping platform experience

Benefits

• Comprehensive medical and healthcare plans
• Company holidays and ETO/FTO programs
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
• Retirement plans varying by region and country
• Competitive salaries