Applications Engineering, Sr Staff Engineer-Physical Design, Synthesis

About the role

We Are Synopsys, the leader in engineering solutions from silicon to systems. We enable customers to rapidly innovate AI-powered products through leading-edge silicon design, IP, simulation, and analysis solutions. Our partnership with customers spans various industries, enhancing their R&D capability and productivity.

Responsibilities

• Diagnose and resolve complex technical issues across the full RTL to GDSII flow on live customer designs, using tools like Fusion Compiler, IC Compiler II, PrimeTime, and StarRC
• Deploy new product releases and advanced node methodologies at customer sites, training design teams on implementation strategies, timing closure techniques, and power optimization workflows
• Work directly with R&D to reproduce customer-reported bugs, validate fixes, and influence the technical roadmap based on real deployment feedback
• Review customer design methodologies and provide recommendations on synthesis strategies, floorplanning approaches, CTS optimization, and signoff closure
• Partner with Sales and customer technical leads to scope proof-of-concept engagements, evaluate design challenges, and build technical solutions that support new account acquisition
• Script automation workflows in Perl, Tcl, or Python to improve customer productivity, streamline debug processes, or replicate complex design scenarios
• Present technical solutions, design trade-offs, and product capabilities to customer engineering teams and management

Qualifications

• Typically requires a bachelor’s degree and a minimum of 8 years of related experience or an advanced degree and a minimum of 6 years of related experience
• Hands-on experience across the full RTL to GDSII flow, including synthesis, place and route, static timing analysis, power analysis, and physical verification
• Strong working knowledge of Synopsys tools such as Fusion Compiler, Design Compiler, IC Compiler II, PrimeTime, StarRC, Formality, or ICC2
• Deep understanding of advanced node design challenges including FinFET effects, multi-patterning, electromigration, and sub-10nm timing closure techniques
• Proficiency in scripting with Perl, Tcl, or Python to automate workflows, parse logs, or build custom analysis flows
• Excellent verbal and written communication skills with the ability to explain timing paths, design trade-offs, and tool behavior to both engineers and management
• Experience in ASIC implementation domains beyond physical design, such as RTL coding, verification, or formal checking, is a plus
• Willingness to travel occasionally to customer sites for deployment, training, or technical escalations