Applications Engineering, Sr. Staff Engineer

About the role

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. At Synopsys, you will work with customers building the chips that power everything, and what you help them solve will show up in products millions of people use.

Responsibilities

• Support pre-sales and post-sales engagements with semiconductor customers, demonstrating Synopsys physical design tools including Fusion Compiler and ICC2 in live technical sessions
• Debug complex physical design issues across the RTL-to-GDSII flow, working directly with customer design teams to resolve placement, routing, timing closure, and congestion challenges at advanced nodes
• Develop and deliver technical methodologies for clock tree synthesis, AI-driven optimization, macro placement, and timing closure that customers can adopt in production flows
• Build proof-of-concept designs and benchmarks that show measurable PPA improvements using Synopsys tools compared to customer baseline flows
• Collaborate with product engineering teams to translate customer pain points into feature requests, tool enhancements, and methodology improvements
• Train customer engineers on advanced Synopsys tool capabilities, from multi-scenario optimization to noise-aware routing techniques
• Travel to customer sites to provide hands-on technical support during critical project phases, including tape-out preparation and bring-up

Requirements

• Bachelor's degree in Electrical Engineering or equivalent with 9+ years of hands-on ASIC physical design experience, or Master's degree with 7+ years
• Deep expertise in RTL-to-GDSII flows using industry-standard tools, with direct experience in placement, optimization, clock tree synthesis, and routing
• Hands-on proficiency with Synopsys backend tools including Fusion Compiler, ICC2, Design Compiler, and PrimeTime
• Strong understanding of advanced node design challenges (7nm and below), including FinFET effects, multi-patterning constraints, and electromigration
• Experience with timing closure techniques, multi-scenario optimization, and noise analysis in complex SoC designs
• Knowledge of clock tree synthesis methodologies including H-Tree and multi-source CTS is a strong plus
• Willingness to travel up to 30% to customer sites for technical engagements and on-site support

Skills

• You can walk into a room where a customer's design is failing timing by 500ps and within an hour identify whether it is a methodology problem, a constraint problem, or a fundamental architecture issue
• You communicate complex technical tradeoffs clearly, whether you are presenting to a staff engineer debugging a routing issue or a director deciding between tool vendors
• You stay calm under pressure, especially when a customer is three weeks from tape-out and needs answers today, not next week
• You are curious about why things break, not just how to fix them, and that curiosity makes you better at preventing problems upstream
• You balance customer advocacy with product reality, pushing back when a request does not make sense but fighting hard when it does
• You enjoy teaching, whether it is walking a junior engineer through CTS fundamentals or showing a principal engineer a technique they have not tried before

Team

You will join the Customer Success Group, the team responsible for helping the world's leading semiconductor companies design and verify advanced silicon chips. This is a technical sales enablement role, which means you will work closely with account teams, product engineers, and directly with customer design teams. The role is based in Sunnyvale, CA, with occasional travel.