Analog Design Engineer (TERADYNE, Agoura Hills, CA)

About the role

Teradyne’s Semiconductor Test Division in Agoura Hills, CA is seeking an Analog Design Engineer to develop high-speed analog and mixed-signal ASICs for Automatic Test Equipment (ATE). The ideal candidate will have experience in CMOS circuit design and successful ASIC tape-outs, along with strong analytical, problem-solving, and communication skills. This role offers the opportunity to collaborate across multidisciplinary teams while leveraging AI-powered tools, automation, and data-driven methodologies to accelerate semiconductor innovation. A passion for emerging technologies, continuous learning, and technical excellence is highly valued.

Responsibilities

• Design and optimize high-speed analog and mixed-signal circuits from specification through transistor-level implementation.
• Validate and integrate designs using Cadence EDA tools across PVT corners, while supporting layout and ASIC integration.
• Participate in silicon characterization, debug, validation, and production test activities.
• Develop automation, scripting, and AI-assisted workflows to improve design productivity, verification, and data analysis.
• Collaborate across design, validation, test, and EDA teams to advance AI-enabled IC design methodologies.

Requirements

• MSEE or higher preferred, with 2+ years of experience in mixed-signal IC design and characterization; FinFET (16nm and below) experience is a plus.
• Strong knowledge of high-frequency analog/mixed-signal IC design, including PLLs, DLLs, ADCs, DACs, VCOs, CDRs, amplifiers, clocking circuits, high-speed I/Os, and CML designs.
• Solid understanding of CMOS device physics, semiconductor processes, PDKs, thermal effects, and electromagnetic principles.
• Experience throughout the IC development lifecycle, including silicon characterization and laboratory measurements.
• Familiarity with AI/ML techniques, generative AI, and large-scale data analysis for semiconductor design, validation, and test applications.
• Proficiency in scripting languages (Python/SKILL/Ocean) for automation and data analysis; Verilog/Verilog-A experience is a plus.

Pay

The base salary range for this role is $127,500 to $204,100. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location. Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

Benefits

• Medical
• Dental
• Vision
• Flexible Spending Accounts
• Retirement savings plans
• Life and disability insurance
• Paid vacation & holidays
• Tuition assistance programs