Analog Design Engineer

About the role

Conduct design and development of image sensor technologies, focusing on transistor-level design of analog and mixed-signal circuits for CMOS Image Sensors. Work includes ASIC pixel arrays, column amplifiers, comparators, ramp generators, ASRAM, and XDEC using Cadence Virtuoso.

Responsibilities extend to whole-chip floorplan design, pad frame creation, and analog/mixed-signal circuit layout design. Collaborate with layout engineers for whole-chip layout integration and improvement, and perform simulations using tools like Analog FastSPICE (AFS), Empyrean ALPS, and NanoSpice.

Conduct design verification (DRC, LVS, PERC) using Siemens Calibre, perform whole-chip IR drop checks with Ansys Totem, and modify scripts using Perl. Work closely with digital engineers to define analog-to-digital interfaces and collaborate with verification, process, test, and application teams to debug and optimize fabricated image sensors.

Analyze project-specific specifications (speed, linearity, noise, power consumption) and improve designs to meet performance requirements. Define corners based on chip operating conditions to ensure reliability and robustness. Propose innovative solutions and advance circuit R&D to stay ahead of current technology.

Requirements

• Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or related field.
• Coursework in Analog Integrated Circuit and Power Electronics Design.
• Skills in analyzing analog and mixed-signal circuits, troubleshooting, and resolving circuit issues.
• Experience designing analog/mixed-signal circuits based on specifications and optimizing for performance.
• Proficiency in circuit simulations using Cadence Spectre or HSPICE.
• Understanding of layout impact on circuit performance and strategies to minimize adverse effects.
• Knowledge of semiconductor device physics and its influence on circuit behavior.
• Ability to analyze and mitigate thermal, flicker, and shot noise in analog designs.
• Familiarity with integrated circuit fabrication processes and process variation considerations.
• Experience designing and analyzing power management circuits, including LDOs and charge pumps.

Pay

Annual base salary for this role in California, US is expected to be between $125,000 - $135,000. Actual pay will be determined based on relevant skills and experience, as well as the pay of employees in similar roles.