Analog Design Engineer

Intel’s Central Engineering Group is seeking an Analog Design Engineer to join the Hard IP and Test Chip Development team. This team delivers industry-defining analog and mixed-signal IP for Intel’s Client, Datacenter, AI, and Foundry customers. The IO team owns high-speed serial IO and die-to-die interfaces across multiple advanced process nodes.

About the role

As an Analog Design Engineer, you will develop cutting-edge analog circuits for advanced process nodes, directly impacting the performance, power efficiency, and area optimization of Intel’s analog and mixed-signal IPs. You will collaborate with cross-functional teams to drive advancements in circuit design and validation, shaping products that redefine technology standards.

Responsibilities

• Design, develop, and build analog circuits for analog and mixed-signal IPs in advanced process nodes.
• Perform circuit analysis using SPICE simulation tools (Cadence, Synopsys, LTSpice, etc.).
• Develop and implement test plans to validate designs against circuit and block microarchitecture specifications.
• Support layout activities and work closely with layout engineers to optimize circuit performance.
• Participate in design reviews and contribute to technical documentation.
• Collaborate with cross-functional teams including architecture, logic design, validation, and SOC partners.
• Perform circuit simulations and debug to ensure power integrity, signal integrity, and leakage reduction.
• Conduct rigorous evaluation of simulation results to optimize circuit designs for power and performance.
• Provide regular reports on design progress to key stakeholders, ensuring transparency and alignment across teams.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 3+ years of experience in circuit design, or Master’s degree in Electrical Engineering, Computer Engineering, or a related field with 2+ years of experience in circuit design.
• Experience with circuit simulation tools and analog behavior modeling.
• Familiarity with signal and power integrity, and layout understanding for analog circuits.
• Knowledge of TX/RX blocks, I/O fundamentals, and core analog design principles, including noise, linearity, matching, and stability.
• Proficiency with Cadence analog IC design tools.

Preferred Qualifications

• IP top-level design experience: Floor Planning, Power Delivery, ESD, Bump Map, Top-Level Sims, Signal Integrity.
• Advanced problem-solving skills with a disciplined approach to execution.
• Experience in group problem-solving and working collaboratively across teams.
• Experience integrating performance, power, and area optimization into circuit designs.
• Mixed-signal design experience.
• Knowledge of layout considerations for analog circuits.
• Experience with scripting languages (Python, MATLAB, etc.).
• Understanding of statistical analysis and design for manufacturability.

Skills

• Strong analytical and problem-solving skills.
• Ability to work independently and make design trade-offs at the transistor level.
• Strong communication skills and ability to provide critical feedback constructively.

Benefits

Intel offers a total compensation package that ranks among the best in the industry, including competitive pay, stock bonuses, and benefit programs such as health, retirement, and vacation.

Pay

Annual salary range for this position in the US: $122,440 – $172,860 USD. Individual pay is determined by job-related skills, experience, and relevant education or training, and may vary by location.

Schedule

This is an on-site role requiring presence in the office at least 4 days per week.