AI Silicon, Junior Digital Design Engineer

Responsibilities

• Contribute to the micro-architecture definition and integration of digital blocks, including CPU, interfaces and memory subsystems.
• Aid in the integration of third-party IP into the main SoC fabric.
• Hands-on RTL Implementation: Write clean, synthesizable, and high-performance Verilog/SystemVerilog code.
• Perform hands-on RTL design for SoC blocks and digital interfaces, focusing on meeting power, performance, and area (PPA) targets.
• Implement and debug key digital interfaces to ensure system stability.
• Implement advanced techniques for low-power design (clock gating, power domains).
• Synthesis & Timing: Perform initial synthesis and formal verification (LEC) to ensure the design is routable and meets frequency targets.
• Create block-level timing constraints.
• Lint & CDC: Run and resolve RTL linting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) checks using industry standard tools.
• Design Verification (DV) Support: Participate in the block-level verification plan and help develop a robust verification environment.
• Triage and debug simulation failures to ensure functional correctness.
• External Coordination: Support created technical interfaces, and assist in the hand-off between internal design and physical implementation teams.

Qualifications

• Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 4+ years of industry experience in digital ASIC/SoC design.
• Strong Technical Expertise: Expertise in Verilog RTL coding and digital design fundamentals.
• Design Flow Proficiency: Familiarity with standard EDA tools for simulation, assertions, synthesis, linting, and clock domain crossing (CDC) analysis.
• Understanding of the full ASIC design flow, from specification to tape-out.
• Communication: Excellent written and verbal communication skills.

Preferred Qualifications

• Experience with design constraints or architectures related to Machine Learning/Neural Network accelerators is a strong plus.
• Experience with UVM (Universal Verification Methodology) environments for basic debugging.
• Knowledge of formal verification techniques.
• Exposure to post-silicon bring-up and lab debugging using logic analyzers or oscilloscopes.
• Experience with modern design methods, including generative AI code development platforms.
• Experience integrating large analog mixed-signal blocks into larger subsystems.

Pay

The salary range for this position is $120,000 - $180,000 annually, commensurate with experience.

Schedule

Full-time, Monday through Friday, 9am to 5pm.

Benefits

Comprehensive benefits package including best-in-class health benefits, 401(k) matching, truly unlimited PTO, and complimentary meals in our Palo Alto office.