AE, RTL2GDS Architect

Key Responsibilities

• Lead technical engagements with customers and partners to achieve best-in-class PPA, working closely with design teams to meet customer success metrics.
• Guide adoption of Cadence’s digital implementation, signoff technologies and AgenticAI features across advanced nodes (3nm and below).
• Partner with R&D and Product Engineering to influence tool enhancements based on real-world customer requirements.
• Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for Synthesis, P&R, STA, IR Drop, and power/timing closure.
• Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader.

Qualifications

• 15+ years of experience in IC design implementation and signoff, with demonstrated success in managing large-scale technical programs.
• BS/MS in Electrical Engineering, Computer Engineering, or related field, with deep expertise in digital design fundamentals, advanced node implementation (3nm and below), and EDA tool ecosystems.
• Proven track record of leading technical teams and driving customer success at executive levels.
• Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure.
• Excellent communication, negotiation, and leadership skills with the ability to influence internal and external stakeholders.
• Prior experience with Cadence tools (Genus, Innovus, Tempus, Voltus, Conformal, Cerebrus) and competitive solutions.

Pay

The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.

Schedule

Not specified.

Benefits

Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.