Advanced Packaging & Integration Engineer

Your Impact

You will operate at the intersection of advanced technology and strategic execution, working within a highly collaborative and cross-functional environment. You will engage directly with counterparts at OSATs, foundries, and key suppliers to drive the development of innovative packaging technologies—specifically focused on heterogeneous integration—from early-stage conceptualization through qualification. This role offers significant cross-organizational visibility and the opportunity to shape critical technology roadmaps and influence long-term product platforms.

Key Responsibilities

• Advanced packaging technology development engineer focused on silicon photonic packaging and electronic-photonic integration, including 2.5D/3D chip stacking, heterogenous integration, and ultra-fine pitch interconnect technologies.
• Drive definition, design and analysis of packaging technology test vehicles. Drive validation of new technology against key performance metrics.
• Apply deep process expertise to oversee wafer processing, fine pitch bumping, D2W/W2W hybrid bonding, fanout, advanced substrate development, and assembly.
• Work with top-tier foundry and assembly partners to develop and qualify robust packaging solutions for high density photonics integration, CPO and on-board optics.
• Utilize design and modeling experience to guide Design for Manufacturability (DfM) and Design for Reliability (DfR).
• Identify and mitigate risks, resolving highly complex packaging issues through advanced root cause analysis and the implementation of corrective actions.

Minimum Qualifications

• PhD or MS in Mechanical Engineering, Electrical Engineering, Physics, or a related field.
• 4+ years of progressive industry experience in advanced packaging with a proven track record of successful project execution in high-density integration.
• Comprehensive knowledge of advanced interconnect materials, process and assembly, including ultra-fine pitch technologies and hybrid bonding.
• Hands-on experience with CAD tools such as kLayout, APD, Solidworks.

Preferred Qualifications

• Knowledge of physical failure analysis methods.
• Hands-on experience with hybrid bonding and thin die/wafer processing.
• Working knowledge of finite element analysis.
• Deep understanding of next-generation substrate and PCB design and materials, and their influence on packaging performance.
• Expertise in si photonic co-integration (CPO, NPO) is a plus.
• Proven ability to work effectively within highly multi-functional and geographically distributed technical teams.

Pay

The starting salary range for this position is $154,900.00 to $225,300.00 for U.S. and/or Canada locations, not including incentive compensation, equity, or benefits. Individual pay is determined by hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. For New York City Metro Area the range is $154,900.00 - $259,100.00; for Non-Metro New York State & Washington State the range is $136,500.00 - $228,300.00. For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Benefits

• Medical, dental and vision insurance.
• 401(k) plan with a Cisco matching contribution.
• Paid parental leave.
• Short and long-term disability coverage.
• Basic life insurance.
• Eligibility for grants of Cisco restricted stock units, vesting following continued employment for defined periods of time.
• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees.
• 1 paid day off for employee’s birthday.
• Paid year-end holiday shutdown.
• 4 paid days off for personal wellness determined by Cisco.
• Non-exempt employees receive 16 days of paid vacation time per full calendar year (accrued at rate of 4.92 hours per pay period for full-time employees).
• Exempt employees participate in Cisco’s flexible vacation time off program with no defined limit (subject to availability and some business limitations).
• 80 hours of sick time off provided on hire date and each January 1st thereafter, with up to 80 hours of unused sick time carried forward from one calendar year to the next.
• Additional paid time away may be requested to deal with critical or emergency issues for family members.
• Optional 10 paid days per full calendar year to volunteer.

Schedule

For sales roles, employees on sales plans earn performance-based incentive pay on top of base salary, split between quota and non-quota components. For quota-based incentive pay, Cisco typically pays as follows: 0.75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.