Advanced ASIC FPGA Verification Engineer (Sign-on Bonus Available)

Basic Qualifications

• Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field
• 5+ years of job-related experience, or a Master's degree and 3 years of job-related experience
• Ability to obtain a U.S. Department of Defense TS/SCI security clearance within a reasonable time from date of hire
• U.S. citizenship required (due to nature of work performed within facilities)

Responsibilities

Duties and Tasks

• Responsible for definition, design, verification and documentation for ASIC and/or FPGA developments
• Determines architecture, system simulation and detailed design approach
• Defines module interfaces and all aspects of device design and simulation
• Creates test and simulation plans that establish functional criteria
• Verifies test results and analyzes performance
• May review vendor capabilities and simulation tools
• Participates in the improvement of the ASIC/FPGA organizational processes
• Supports the generation of technical engineering products using appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle
• May provide leadership and/or direction to lower level employees
• Independently determines approach to solutions
• Contributes to the completion of major programs and projects
• Plans and executes project tasks for activities described above

General Knowledge, Skills and Abilities

• Ability to operate in a team environment and learn new skills to accomplish verification goals
• Proficient use and understanding of ASIC/FPGA engineering concepts, principles, and theories
• Proficient in the principles and techniques of ASIC/FPGA design and the design process
• Keeps abreast of technology trends
• Proficient awareness of business objectives and Engineering’s role in achieving them
• Proficient in Microsoft Office applications
• Proficient written and verbal communications skills
• Ability to think creatively and multi-task
• Proficient skill in communicating issues, impacts, and corrective actions
• Regular contact with senior levels of internal work groups
• Works under limited direction
• Contact with project leaders and other professionals within the Engineering department and with project teams across the company
• Some contact with external customers

Preferred Qualifications

Primary Job Qualifications (Preferred Skills/Experience)

• In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment
• In-depth knowledge of System Verilog object oriented programming and the Universal Verification Methodology (UVM)
• Understands UVM Testbench Architectures
• Comfortable using and developing UVM agents, bus functional models
• Understands different types of coverage, usage of cover classes, cover points, etc.
• Experience with predictive testbench components, functional coverage and assertions
• Experience with constrained random testing
• Experience with the Register Abstraction Layer
• Familiarity with requirements-based verification, requirement tracing, and developing requirement verification strategies
• Experience with scripting languages such as Linux shell scripts, TCL, Python
• Familiarity with using Formal Verification tools, code coverage, writing waivers
• Familiarity with Questa Verification IP (QVIP)
• Developing UVM testbenches for designs implemented in Xilinx devices with Xilinx IP and SoCs
• AXI protocols, PCIe, Space Wire, and Ethernet interfaces
• DSP functions and common signal processing components
• Familiar with debugging FPGA/ASIC hardware and assisting with HW/SW integration
• Continuous Integration features of GITLab

What Sets You Apart

• Clear understanding of embedded micro-processing systems, FPGA Design and Verification using VHDL, and digital circuit analysis and design
• Collaborative, creative thinker with high proficiency in technical problem solving
• Team player with effective communication and presentation skills
• Experience designing high speed interfaces and complex memory designs
• Commitment to ongoing professional development for yourself and others
• Identifies opportunities to apply AI for continuous improvement and innovation

Benefits & Work Schedule

• Flexible schedules with every other Friday off (9/80 schedule), if desired
• Competitive benefits including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, employee resource and social groups
• Exciting career path with opportunities for continuous learning and development
• Research oriented work alongside award winning teams developing practical solutions for national security

Workplace Options

This position is fully remote, on-site, or hybrid/flex, as mutually agreed. You will be part of the Scottsdale, AZ team.

Pay

Target salary range: USD $122,785.00/Yr. - USD $136,215.00/Yr. This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary.

About General Dynamics Mission Systems

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. We value trust, honesty, alignment and transparency, offer highly competitive benefits, and pride ourselves on being a great place to work with a shared sense of purpose.

Key Words: Verification, ASIC, FPGA, SystemVerilog, Verilog, Assertions (SVA), OVM, UVM, Digital Signal Processing (DSP), functional coverage, constrained random, formal verification, constrained random testing